The present invention relates to reducing latency, and more specifically, to reducing latency in Ethernet systems with multiple clock domains. The Ethernet physical layer is developed according to the Open Systems Interconnection (OSI) model. Several layers are defined in the various Ethernet standards, including the Physical Layer (PHY). The Ethernet Physical Coding Sublayer (PCS) is part of the Ethernet PHY layer and performs autonegotiation, coding, and other functions.
Latency is a critical parameter in many networking applications, such as financial applications. 40G and 100G Ethernet is more complex than 10G Ethernet, in part due to 64b/66b line coding instead of 8b/10b. Typical Ethernet implementations follow the IEEE functional definition which includes three clock domains (Media Access Control (MAC) Interface, PCS Core, and Link Interfaces). In addition, multiple data reformattings are performed. These data reformattings and clock boundary crossings contribute to a relatively large amount of latency in the system.